1. Field of the Invention
The present invention relates to a display device, and more particularly, to an organic electro luminescence device that has an improved image quality.
2. Discussion of the Related Art
In general, an organic electro luminescence device, which also is referred to as an organic light emitting diode (OLED) device, includes a plurality of pixels and an organic light emitting diode in each of the pixels. Each of the organic light emitting diodes has a cathode electrode injecting electrons, an anode electrode injecting holes, and an organic electro-luminescence layer between the cathode and anode electrodes. Each of the organic light emitting diodes generally has a multi-layer structure of organic thin films formed between the anode electrode and the cathode electrode. When a forward current is applied to the organic thin films, electron-hole pairs (often referred to as excitons) are combined in the organic thin films as a result of a P-N junction between the anode electrode and the cathode electrode. The electron-hole pairs have a lower energy when combined together than when they were separated. Thus, the resultant energy gap between the combined and separated electron-hole pairs is converted into light by an organic electro-luminescent layer. In other words, the organic electro-luminescent layer emits the energy generated due to the recombination of electrons and holes in response to an applied current.
Thus, organic electro luminescence devices do not need an additional light source. In addition, organic electro luminescence devices are thin, light weight, and energy efficient, and have a low power consumption, high brightness, and short response time. Because of these advantageous characteristics, the organic electro luminescence devices are regarded as a promising candidate for various next-generation consumer electronic appliances, such as mobile communication devices, personal digital assistance (PDA) devices, camcorders, and palm PCs. Also, the fabrication of organic electro luminescence devices is a relatively simple process, thereby reducing fabrication costs.
An organic electro luminescence device is categorized as a passive matrix type or an active matrix type. The passive matrix type organic electro luminescence device has a relatively simple structure and fabrication process, but requires higher power in comparison to the active matrix type. In addition, the passive matrix type organic electro luminescence device has a larger size and has a poor aperture ratio as the bus lines therein increase. On the contrary, in comparison to the passive matrix type, the active matrix type organic electro luminescence device provides a higher display quality with higher luminosity.
FIG. 1 is a schematic diagram of an active matrix type organic electro luminescence device according to the related art. In FIG. 1, an active matrix type organic electro luminescence device includes a plurality of scan lines S1 to Sm along a first direction, and a plurality of data lines D1 to Dn along a second direction intersecting the scan lines S1 to Sm, thereby defining a plurality of pixel regions. An organic light emitting diode E, a switching thin film transistor (TFT) P1, a driving TFT P2, and a capacitor C1 are formed within each of the pixel regions. The switching TFT P1 and the driving TFT P2 are p-type metal oxide semiconductor (PMOS) transistors. In particular, a gate and a source of the switching transistor P1 are respectively connected to one of the scan lines S1 to Sm and one of the data lines D1 to Dn. A drain of the switching transistor P1 is connected to the capacitor C1. A source and a drain of the driving transistor P2 are connected to a power VDD and an anode of the organic light emitting diode E, respectively. Further, a gate of the driving transistor P2 is connected to the drain of the switching transistor P1.
In addition, when a scan signal is applied to the gate of the switching transistor P1 through the scan line S, the switching transistor P1 is turned on. At this time, a data voltage applied to the data line D is transmitted to the capacitor C1 through the switching transistor P1, thereby charging the capacitor C1. Thereafter, the driving transistor P2 is operated, and then the charge stored in the capacitor C1 determines current level that flows into the organic light emitting diode E through the driving transistor P2.
As a result, the organic light emitting diode E can display a gray scale between black and white. In particular, the scan lines S1 to Sm are sequentially driven to turn on the switching transistors P1 connected to the corresponding scan line, and then data voltages are applied to the desired data lines to operate the respective organic light emitting diode E.
FIG. 2 is a circuit diagram of a pixel region of an organic electro luminescence device according to the related art. As shown in FIG. 2, four transistors, instead of two transistors shown in FIG. 1, are formed in a pixel region. The four-transistor structure shown in FIG. 2 is often referred to as 4-TFT/1-CAP. In FIG. 2, a data line D and a power line VDD are formed along a first direction, and a first scan line Sc1 and a second scan line Sc2 are formed along a second direction intersecting the data line D and the power line VDD, thereby defining the pixel region. First and second driving TFTs M1 and M2, a organic light emitting diode E, first and second switching TFTs SW1 and SW2, and a storage capacitor Cst also are formed in the pixel region.
The first and second driving TFTs M1 and M2 receive a power voltage from the power line VDD, and the second driving TFT M2 is connected to the organic light emitting diode E. The first and second switching TFTs SW1 and SW2 receive scan signals from the first and second scan lines Sc1 and Sc2, respectively. The first switching TFT SW1 receives a data signal from the data line D, and the second switching TFT SW2 receives output signals from the first switching and driving TFTs SW1 and M1. The storage capacitor Cst is connected between the power line VDD and gates of the first and second driving TFTs M1 and M2, and supplies a voltage to the gates of the first and second driving TFTs M1 and M2 to maintain the voltage signals thereof.
The first switching TFT SW1 is an n-type metal oxide semiconductor (NMOS) transistor, and the second switching TFT SW2, the first driving TFT M1, and the second driving TFT M2 are PMOS transistors. Further, the first and second driving TFTs M1 and M2 form a current mirror circuit, such that the drain current of the first driving TFT M1 is proportional to the drain current of the second driving TFT M2 irrespective of a load resistance value. As a result, the current mirror circuit controls the organic light emitting diode E, such that a mirror ratio (MR) of the second driving TFT M2 and the first driving TFT M1 controls the current level being applied to the organic light emitting diode E.
FIG. 3 is a graph showing scan signals applied to the scan lines Sc1 and Sc2 of FIG. 2, and FIGS. 4A and 4B are equivalent circuit diagrams illustrating ON and OFF states of the device of FIG. 2. As shown in FIG. 3, a high-state scan signal is applied to the first scan line Sc1 and a low-state scan signal is applied to the second scan line Sc2 during a pre-charging period. In addition, the low-state scan signal of the second scan line Sc2 is switched to a high-state at the end of a Cst charging period, before the high-state scan signal of the first scan line Sc1 is switched to a low-state.
When the high-state scan signal is applied to the first scan line Sc1 and when the low-state scan signal is applied to the second scan line Sc2 during the pre-charging period and during the Cst charging period, the first and second switching TFTs SW1 and SW2 are turned on. As shown in FIG. 4A, when the first and second switching TFTs SW1 and SW2 are turned on, the first driving TFT M1 functions as a diode. Therefore, a current IOLED applied to the second driving TFT M2 is controlled by a data current Idata of the first driving TFT M1. For example, if the first and second driving TFTs M1 and M2 are in a mirror ratio (MR) of 5:1 and if the OLED E needs a current of 1 microampere (μA) to display a white color, then a current of 1 microampere (μA) can be applied to the organic light emitting diode E through the second driving TFT M2 when a current of 5 microamperes (μA) is sunk through the first driving TFT M1.
In addition, as shown in FIG. 4B, the pixel has a current sink method, such that gate voltages Vg_m1 and Vg_m2 of the first and second driving TFTs M1 and M2 have the same value irrespective of elements of the neighboring pixels. Therefore, the pixel having the structure of FIG. 2 can improve the image quality, and the charge stored in the storage capacitor Cst can maintain the voltage of the voltage signal on the gates of the driving TFTs M1 and M2. Additionally, although the switching TFTs SW1 and SW2 are turned OFF, the current level flowing to the organic light emitting diode E remains constant during one frame.
FIG. 5 illustrates parasitic capacitances in the pixel of FIG. 2. As shown in FIG. 5, a first parasitic capacitance C1 is between the first switching TFT SW1 and the gates of the first and second driving TFTs M1 and M2. A second parasitic capacitance C2 is between the second switching TFT SW2 and the gates of the first and second driving TFTs M1 and M2. As a result, after switching off the first and second switching TFTs SW1 and SW2, a kick back phenomenon occurs. First and second kick back currents caused by the first and second parasitic capacitances C1 and C2 can be calculated by the following equations (1) and (2).
                              Δ          ⁢                                          ⁢          Ip          ⁢                                          ⁢          1                =                                            C              ⁢                                                          ⁢              1                                                      C                ⁢                                                                  ⁢                1                            +                              C                ⁢                                                                  ⁢                2                            +              Cst                                ⁢          Δ          ⁢                                          ⁢          I          ⁢                                          ⁢          1                                    Equation        ⁢                                  ⁢                  (          1          )                                                  Δ          ⁢                                          ⁢          Ip          ⁢                                          ⁢          2                =                                            C              ⁢                                                          ⁢              2                                                      C                ⁢                                                                  ⁢                1                            +                              C                ⁢                                                                  ⁢                2                            +              Cst                                ⁢          Δ          ⁢                                          ⁢          I          ⁢                                          ⁢          2                                    Equation        ⁢                                  ⁢                  (          2          )                    where C1 is the first parasitic capacitance between the first switching TFT SW1 and the gates of the first and second driving TFTs M1 and M2, and C2 is the second parasitic capacitance between the second switching TFT SW2 and the gates of the first and second driving TFTs M1 and M2. Furthermore, ΔI1 and ΔI2 represent current values applied to the first and second parasitic capacitors C1 and C2.
FIG. 6 is a simulation graph illustrating kick back currents occurring in the pixel of FIG. 2. As shown in FIG. 6, when the second and first switching TFTs SW2 and SW1 (shown in FIG. 2) are sequentially turned off, the parasitic capacitances C1 and C2 induce a voltage drop producing the current drop at portions A and B. The overall kick back current ΔIp may be about 27.1% of the total current. As a result, the organic electro luminescence device displays abnormal lines during operation.
FIG. 7 is a circuit diagram of a pixel of another organic electro luminescence device according to the related art. In FIG. 7, the pixel includes a data line D, a power line VDD, first and second driving TFTs M1 and M2, a organic light emitting diode E, first and second switching TFTs SW1 and SW2, first and second scan lines Sc1 and Sc2, and a storage capacitor Cst. The first and second driving TFTs M1 and M2 receive a power voltage from the power line VDD. The second driving TFT M2 is connected to the organic light emitting diode E.
The first and second switching TFTs SW1 and SW2 receive scan signals from the first and second scan lines Sc1 and Sc2, respectively. The first switching TFT SW1 is connected to the data line D to receive a data signal from the data line D. The second switching TFT SW2 is connected to the first switching and driving TFTs SW1 and M1. The storage capacitor Cst is located between the power line VDD and a drain of the second switching TFT SW2, and supplies a voltage to the gate of the second driving TFTs M2.
Unlike the pixel shown in FIG. 2, the first and second switching TFTs SW1 and SW2 and the first and second driving TFTs M1 and M2 of FIG. 7 are PMOS transistors. An anode of the organic light emitting diode E is connected to the second driving TFT M2.
The first and second driving TFTs M1 and M2 has a connection of current mirror circuit where the drain current of the first driving TFT M1 is proportional to the drain current of the second driving TFT M2 irrespective of the load resistance value. In FIG. 7, the anode of the organic light emitting diode E is connected to a drain of the second driving TFT M2, such that the current mirror circuit controls the data value applied to the organic light emitting diode E. As a result, the mirror ratio (MR) of the second driving TFT M2 and the first driving TFT M1 controls the current level being applied to the organic light emitting diode E.
FIG. 8 is a graph showing scan signals applied to the scan lines Sc1 and Sc2 of FIG. 7, and FIGS. 9A and 9B are equivalent circuit diagrams illustrating ON and OFF states of the switching elements of FIG. 7. As shown in FIG. 8, a low-state scan signal is applied to both the first and second scan lines Sc1 and Sc2 during a pre-charging period. Then, a high-state scan signal is applied to the second scan line Sc2 at the end of a Cst charging period, before another high-state scan signal is applied to the first scan line Sc1.
As shown in FIG. 9A, when the low-state scan signals are applied to the first and second scan lines Sc1 and Sc2, the first and second switching TFTs SW1 and SW2 are turned ON. Thus, the current sink is formed, gate voltages Vg_m1 and Vg_m2 of the first and second driving TFTs M1 and M2 are the same.
As shown in FIG. 9B, when the first and second switching TFTs SW1 and SW2 are turned OFF, the first and second driving TFTs M1 and M2 receive the different gate voltages. Therefore, the different stresses are imposed on the first and second driving TFTs M1 and M2, and those driving TFTs M1 and M2 express different characteristics. For example, when the first and second switching TFTs SW1 and SW2 are turned OFF, the second gate voltage Vg_m2 of the second driving TFT M2 is the data voltage from the data line D, but the first gate voltage Vg_m1 of the first driving TFT M1 is a difference between a power VDD and a threshold voltage Vth-m1 of the first driving TFT M1 because of the continuous diode connection. Thus, the first and second gate voltages Vg_m1 and Vg_m2 are significantly different from each other. As a result, the organic electro luminescence device still fails to uniformly display images.
FIG. 10 illustrates a parasitic capacitance in the pixel of FIG. 7. As shown in FIG. 10, a parasitic capacitance C3 is formed between the gate of the second driving TFT M2 and a gate terminal of the second switching TFT SW2. As a result, after switching off the first and second switching TFTs SW1 and SW2, a kick back phenomenon occurs. A kick back current caused by the parasitic capacitance C3 can be calculated by the following equation (3).
                              Δ          ⁢                                          ⁢          Ip          ⁢                                          ⁢          3                =                                            C              ⁢                                                          ⁢              3                                                      C                ⁢                                                                  ⁢                3                            +              Cst                                ⁢          Δ          ⁢                                          ⁢          I          ⁢                                          ⁢          3                                    Equation        ⁢                                  ⁢                  (          3          )                    where C3 is a parasitic capacitance between the second switching TFT SW2 and the second driving TFT M2, and ΔI3 represents a current value applied to that parasitic capacitor C3.
FIG. 11 is a simulation graph illustrating a kick back current occurring in the pixel of FIG. 7. As shown in FIG. 11, when the second and first switching TFTs SW2 and SW1 (shown in FIG. 7) are sequentially turned off, the parasitic capacitance C3 (shown in FIG. 10) induces a voltage drop producing the current drop at portion A. The overall kick back current ΔIp3 may be about 6.1% of the total current. However, the organic electro luminescence device still fails to uniformly display images because the first and second driving TFTs M1 and M2 receives different electrical stresses as the first and second switching TFTs SW1 and SW2 are turned off.